Heavy capacitive loads are very common in industrial and commercial systems and equipment. A common example is a piezoelectric element which is used extensively in such applications as ink jet printers, speakers and motor drives. A piezoelectric element, formed by piezoelectric material sandwiched between two electrodes, is typically electrically modeled as a large capacitor, with the piezoelectric material acting as both a dielectric between the electrodes and an actuator under the influence of the electric field resulting from the application of a voltage across the electrodes. Indeed, an entire matrix of piezoelectric actuators for individual droplet making mechanisms in an inkjet printer head may be modeled as a single capacitive load. Throughout this application, unless otherwise expressly stated, discussion of a capacitive load in the form of a piezoelectric actuator will be understood to also include a matrix of such actuators, producing a single capacitive load to which an output voltage is applied, and that this capacitive load also has typically resistive and inductive components to it. The operation of load drive circuits for other loads with high capacitance and with added inductance, such as in an LC tank circuit may be improved with embodiments of the present invention.
The electrical drive to the capacitive load, such as a piezoelectric actuator, may be a controlled high voltage waveform delivered, as an example once per cycle of printer head operation or the like. The shape, period, and frequency of this waveform can be heavily dependent upon the application. Such loads may have, as is the case with most piezoelectric element drive waveforms, fast switching transitions.
Therefore, typically a fast linear high voltage (HV) amplifier is used to deliver the waveform to the piezoelectric element. In such a fast linear high voltage (HV) amplifier, power dissipated while switching a load capacitor between a ground voltage GND to the high voltage VDD (as an example 50 V) is given by:PDISS=CL·VDD2·f  (1)where CL=Load Capacitor capacitance, f=Frequency of drive waveform.
Existing linear capacitive load drives conform to equation 1. This relationship can result in limitations on attributes of the application or engineering system, such as maximum load capacitance and frequency of the waveform. This relationship can further limit the number of actuators that can be driven, such as in the piezoelectric inkjet printer print head application, the number of inkjets and thereby the resolution of the printing by the print head, as well as the speed of printing, i.e., cycles per second of actuation. Achieving higher resolution by being able to drive more inkjets and higher frequency of the drive voltage waveform is generally desirable. In inkjet printer piezoelectric applications, faster operation is always a goal resulting in faster printing speed.
FIG. 1 shows a schematic diagram of a circuit 10 useful in understanding energy dissipation while driving a capacitive load CLOAD 20. FIG. 1 shows two switches 22, 24 for charging and discharging the capacitor CLOAD 20. The circuit 10 includes a voltage supply 26, such as a 50 V DC power supply, which when voltage controlled switch 22 is closed, charges the load capacitor 20 through a resistor 28 that is modeling ON resistance of the switch, and a voltage controlled switch 24, which when closed, discharges the load capacitor 20 through a resistor 30 to ground. Each of the switches 22, 24 has a respective switch voltage supply 40, 42 to assist in the control of the timing and operation of the respective switches.
FIG. 1 shows switch 22, that when closed, charges the load capacitor 20 with a charge Q=CLOAD×VDD. The energy from the supply 26 to provide this charge is ESUPPLY=Q×VDD=CLOAD·VDD2. The energy stored in the capacitor 20 is Ec=CLOAD·×VDD2/2. These results can also be derived by integrating the instantaneous power over the period of interest.
                                          E            SUPPLY                    =                                    ∫              0              ∞                        ⁢                                                                                i                    VDD                                    ⁡                                      (                    t                    )                                                  ·                                                      V                    DD                                    ⁡                                      (                    t                    )                                                              ⁢                                                          ⁢                              ⅆ                t                                                                                  =                                    C              L                        ·                          V              DD                        ·                                          ∫                0                ∞                            ⁢                                                                                                        ⁢                                                            ⅆ                                              V                        OUT                                                              ·                                          ⅆ                      t                                                                                        ⅆ                  t                                                                                                  =                                    C              L                        ·                          V              DD                        ·                                          ∫                0                50                            ⁢                              ⅆ                                  V                  OUT                                                                                                  =                                                    C                L                            ×              50              ×              50                        =                          2500              ·                              C                L                                                                                                  E            C                    =                                    ∫              0              ∞                        ⁢                                                            i                  dd                                ⁡                                  (                  t                  )                                            ·                                                v                  out                                ⁡                                  (                  t                  )                                            ·                                                          ⁢                              ⅆ                t                                                                                  =                                    C              L                        ·                                          ∫                0                ∞                            ⁢                                                                                                                                  ⁢                                          ⅆ                                                                        v                          OUT                                                ⁡                                                  (                          t                          )                                                                                                                          ⅆ                    t                                                  ·                                                      V                    OUT                                    ⁡                                      (                    t                    )                                                  ·                                  ⅆ                  t                                                                                                              =                                                            C                  L                                ·                                                      [                                                                  v                                                  OUT                          2                                                                    2                                        ]                                    0                  50                                            =                              1250                ·                                  C                  L                                                              ⁢                                          ⁢                                    E                              diss                ⁢                                                                  ⁢                1                                      =                                                            E                  SUPPLY                                -                                  E                  C                                            =                              1250                ·                                  C                  L                                                                        
This analysis shows that half of the energy supplied by the voltage source is stored in the load capacitor while the other half is dissipated in switch 22 and resistor 28. During the discharge phase, the charge is removed from CLOAD 20, and the energy is dissipated in switch 24 and resistor 30. Thus the energy dissipated during each switching cycle is given by:Ediss=CLOAD·VDD2=2500·CLOAD(VDD=50V)  Equ (1)
Adiabatic switching has been done at low voltages in digital circuits as discussed in the following references. Indermaur et al., Evaluation of Charge Recovery Circuits and Adiabatic Switching for Low Power CMOS Design, IEEE Symposium on Low Power Electronics (1994), relates to charge recovery through adiabatic switching (from rail high or low voltage to the other rail voltage over sequential rails) for power reduction in CMOS integrated circuits. Gabara, Pulsed Power Supply CMOS—PPS CMOS, IEEE Symposium on Low Power Electronics (1994), relates to similar ramped driving and charge recovery, called “pulsed power” in CMOS circuits. Similarly Svensson et al., Driving a Capacitive Load Without Dissipating fCV2, IEEE Symposium on Low Power Electronics (1994), describes a similar “stepwise charging” in CMOS circuits.
While existing systems are of great benefit, there is always a need to improve performance of capacitive load drive systems, such as a piezoelectric drive system, including performance in energy savings, improved speed of operation, ability to drive more load elements which would allow for increased resolution of inkjet printing. Accordingly, there is a need in the art for a more effective and efficient drive circuit.